by Mat Dirjish
Micro- and nano-technologies research institute CEA-Leti and CEA-List, a specialist in smart digital systems, are collaborating with Powerchip Semiconductor Manufacturing Corp. (PSMC) to introduce high-bandwidth communication and high-efficiency computing technologies into PSMC’s 3D stacking and interposer platforms. Their goal is to deliver solutions for next-generation artificial intelligence (AI) systems.
Reportedly, semiconductor makers face challenges that include the physical limits of traditional copper interconnects, stringent power budgets, and the need for flexible, scalable computing architectures. Integrating short-reach, high-bandwidth optical links for energy-efficient data movement and customizable RISC-V processor architectures addresses these constraints by creating a paradigm in high-performance data transport and computing architectures.
Olivier Thomas, Deputy Head of the Digital IC Design Division at CEA-List, explains, “RISC-V is transforming processor design by combining openness, flexibility, and cost efficiency. Its customizable architecture allows industrial players to develop solutions tailored to their needs.” Sébastien Dauvé, Chief Executive Officer of CEA-Leti, adds, “In the collaboration, microLED is a critical enabling technology that will boost optical-communication throughput using low-power GaN LED solutions.”
As per Dr. Shou-Zen Chang, Chief Technology Officer of PSMC, the collaboration enriches PSMC’s 3D stacking and interposer technology envelope with high-efficiency RISC-V computing IP and high-bandwidth silicon photonics chiplet communication. “By leveraging the expertise of CEA-Leti and CEA-List alongside PSMC’s technologies, we will provide foundry services for next-generation AI applications.”
Mat Dirjish Online 